RTL Engineer
Quick facts
- Pay
- $215,000 - $300,000 USD
- Type
- Full-time
- Location
- Mountain View, CA
- Skills
- Python
- Industry
- Engineering — 264 open jobs
- Visa in listing
- H-1B, OPT
- Apply
- Free to apply — never pay anyone for a job offer or visa sponsorship
Job description
About the role
Design the RTL that defines our AI accelerator. You'll architect and implement the digital blocks — compute datapath, memory subsystem, on-chip interconnect, and control logic — from microarchitecture spec through synthesis-ready, timing-clean RTL, and own those blocks end-to-end with architecture, DV, physical design, and DFT all the way to silicon.
What You'll Do:
- Own RTL design of digital blocks/subsystems for our accelerator — microarchitecture definition, SystemVerilog implementation, and integration
- Translate architectural specs into efficient, synthesizable RTL that meets power/performance/area (PPA) targets
- Drive microarchitecture trade-offs — pipelining, datapath vs. control, clock/power gating — for high-performance, low-power design
- Partner with DV on verification, PD on synthesis/timing/floorplan closure, and DFT on testability
- Own block-level quality: synthesis, timing/constraints (SDC, STA), lint, and CDC signoff
- Contribute to architecture definition and design reviews; debug across simulation, emulation, and post-silicon bring-up
- Use and develop AI-assisted tool flows to accelerate design and verification
What We're Looking For
- Strong digital-design fundamentals and expert Verilog/SystemVerilog RTL
- 5+ years designing complex digital blocks/SoCs taken to silicon
- Solid microarchitecture skills — pipelining, datapath/control, FIFOs, arbitration, memory subsystems, on-chip interconnect/NoC
- Synthesis & timing awareness — writing synthesizable RTL, SDC constraints, STA, clock/power gating, CDC, lint
- Demonstrated collaboration with DV, PD, and DFT across the full RTL2GDS flow to tapeout
- Scripting (Python/Tcl/) for design automation
- (Optional) AI/ML accelerator or high-performance compute-datapath design; low-power techniques (UPF); high-speed interfaces (HBM, PCIe, SerDes); advanced nodes (7nm or better); RISC-V/CPU design; FPGA prototyping
Compensation
Final offers depend on level, location, and skills relevant to the role. Additional compensation: equity grant per company guidelines; medical / dental / vision; 401(k); standard PTO.
Visa Sponsorship
DensityAI sponsors qualified candidates for H-1B, O-1, TN, E-3, and other employment-based visas, and we welcome applicants on F-1 OPT and STEM-OPT. Work authorization is required at start; we provide immigration support to secure or transfer status.
Export Controls
Aspects of this role may involve access to information subject to U.S. export controls (EAR/ITAR). We may discuss licensing or scope adjustments during the interview.
Equal Opportunity
DensityAI is an Equal Opportunity Employer. We do not discriminate on the basis of race, color, religious creed, national origin, ancestry, physical or mental disability, medical condition, genetic information, marital status, sex, gender, gender identity, gender expression, age (40+), sexual orientation, military or veteran status, pregnancy, or any other status protected by law. We comply with the California CROWN Act and provide reasonable accommodations on request.
Full compensation packages are based on candidate experience and relevant certifications.
California pay range
$215,000 - $300,000 USD
Compensation
Final offers depend on level, location, and skills relevant to the role. Additional compensation: equity grant per company guidelines; medical / dental / vision; 401(k); standard PTO.
Visa Sponsorship
DensityAI sponsors qualified candidates for H-1B, O-1, TN, E-3, and other employment-based visas, and we welcome applicants on F-1 OPT and STEM-OPT. Work authorization is required at start; we provide immigration support to secure or transfer status.
Export Controls
Aspects of this role may involve access to information subject to U.S. export controls (EAR/ITAR). We may discuss licensing or scope adjustments during the interview.
Equal Opportunity
DensityAI is an Equal Opportunity Employer. We do not discriminate on the basis of race, color, religious creed, national origin, ancestry, physical or mental disability, medical condition, genetic information, marital status, sex, gender, gender identity, gender expression, age (40+), sexual orientation, military or veteran status, pregnancy, or any other status protected by law. We comply with the California CROWN Act and provide reasonable accommodations on request.
Full compensation packages are based on candidate experience and relevant certifications.
Visa sponsorship record
No public sponsorship records foundWe didn't find H-1B, H-1B1, E-3 or green card (PERM) filings under the name DensityAI in the Department of Labor and USCIS data. That doesn't mean the job can't be sponsored — the company may file under a different legal name, be new to sponsorship, or sponsor a visa that isn't in these datasets (for example H-2B or J-1).
Tip: ask the recruiter early, in writing, which visa they sponsor and whether they cover the legal and filing fees.
Which visas can work for this job
Occupation: Engineers, All Other (SOC 17-2199) — estimated from the job title.
- Mentioned in the listing
H-1B, OPT
- H-1B cap-exempt employer
Regular cap-subject employer — a new H-1B needs to win the lottery in March (unless you already hold cap-counted H-1B status).
- TN (citizens of Canada and Mexico)
This kind of role may fit the USMCA profession “Engineer” — it depends on the actual duties. No lottery, no cap; you need the matching degree or license.
- E-3 (Australia) and H-1B1 (Chile, Singapore)
Same degree requirement as H-1B, but no lottery and a separate quota that is rarely filled.
- O-1 (extraordinary ability)
For candidates with awards, publications, press, a high salary or critical roles at distinguished organizations. No cap, no lottery; the employer files a petition.
- STEM OPT extension (F-1 students)
Requires an E-Verify employer. We didn't find this company in the E-Verify list — ask HR.
Salary vs prevailing wage
Level IV (fully competent)Engineers, All Other · San Jose-Sunnyvale-Santa Clara, CA. Annual prevailing wages set by the Department of Labor (OFLC).
| Level | Prevailing wage | H-1B lottery odds* |
|---|---|---|
| Level I | $105,664 | ~15% |
| Level II | $138,237 | ~31% |
| Level III | $170,830 | ~46% |
| Level IV | $203,403 | ~61% |
This job pays $215,000–$300,000 a year — that's Level IV (fully competent). In the wage-weighted H-1B lottery a Level IV registration gets 4 entries; estimated selection chance about 61% — better than average.
* Odds are DHS projections for the FY2027 wage-weighted lottery (actual results vary by year and employer). Since the FY2027 cap season the H-1B lottery is weighted by wage level: Level I = 1 entry, II = 2, III = 3, IV = 4. The level is set by the offered wage against the prevailing wage for the occupation and worksite. Separately, a $100,000 fee for new H-1B petitions for workers outside the US was announced in 2025; as of September 2026 a federal court ruling keeps it unenforceable while appeals continue — check the current status.
Sources: U.S. Department of Labor OFLC disclosure data (H-1B/H-1B1/E-3 LCA, PERM), OFLC prevailing wage data, USCIS H-1B Employer Data Hub, E-Verify participating employers. Data loaded: LCA FY2024–FY2026, PERM, USCIS Data Hub, OFLC wages; updated 2026-10-03. Employers are matched by name, so records of companies with similar names can occasionally be mixed up. This is general information, not legal advice — talk to an immigration attorney about your case.